The command and address terminals may be supplied with command signals CMD, address signals ADDR, and chip selection signals CS, from a memory controller. The command signals may represent various memory commands from the memory controller (e.g., including access commands, which can include read commands and write commands). The select signal CS may be used to select the memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device 100, the commands and addresses can be decoded and memory operations can be performed. The command signals CMD can be provided as internal command signals ICMD to a command decoder 115 via the command/address input circuit 105. The command decoder 115 can include a processor 116 and/or other circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations. For example, the processor 116 can execute the instructions to and/or other circuits can be configured to generate row and column command signals and/or the associated timing signals (e.g., in coordination with the timing generator 135) to select a word line and/or a bit line to perform the desired memory operation. Of course, the processor/circuitry to generate the command and/or timing signals can be located in another component of the memory device 100 such as, for example, address command input circuit 105 and/or an external controller/processor. The internal command signals can also include output and input activation commands, such as clocked command CMDCK.