The RFX_n signal can be set to high state (e.g., corresponding to time t0 in FIG. 3B) to select the pertinent memory bank and/or the corresponding one or more MWDs for operation. In some embodiments, when RFX_n is in the high state, the timing signals RMSWMP and RMSXDP are also set to the high state. With the RFX_n and RMSWMP signals at the high state, the output of NAND gate circuit 312 is low, which means the RFF signal is low. A low signal value on RFF means that the ARMW signal is connected to the global word line GR in MWD 300. In addition, a low signal value on RFF means that NMOS transistor 326 is OFF to isolate Voff from node 321. With RFF low, PMOS transistor 320 is turned ON to pull up node 321 and thus the RF signal high to the voltage V 1. In some embodiments, V1 can be 2.5 volts and the RF signal can be pulled up to a value of 2.5 volts. With the RFX_n and RMSXDP signals at the high state, the NMOS transistor 322 is ON but because NMOS transistor 326 is OFF, the node 321 remains isolated from the voltage source Voff. To prevent unreliable operation, a continuously gated NMOS transistor 324 is provided in series between NMOS transistor 322 and NMOS transistor 326. The NMOS transistor 324 has a gate voltage Von that is sufficient to keep transistor 324 continuously gated. The inclusion of continuously gated transistor 324 provides more reliability to the RF driver circuit 310 by providing a resistive path for the leakage current going through NMOS transistor 326 to create a voltage drop in the leakage current path when the NMOS transistor 326 is OFF.