In some embodiments, when row hammer stress mitigation is desired, the RMSXDP signal remains high for a predetermined period (e.g., from time t1 to t2, see FIG. 3B) to allow for a “soft landing” for the RF voltage and thus the global word line voltage GR. As discussed below, a “soft landing” on the global word line GR also means a “soft landing” on the local word line WL to mitigate the row hammer stress between adjacent local word lines WL in a memory bank MB. To mitigate the row hammer stress, the global word line GR is stepped down to an intermediate voltage Voff prior to entering the pre-charge or standby state. This is accomplished by having the global word line GR follow the RF signal for a predetermined time period (e.g., between t1 and t2, see FIG. 3B). For example, with the RMSXDP and RFX_n signals in the high state, the output of AND gate circuit 314 remains at a high state to keep NMOS transistor 322 ON. With NMOS transistors 322, 324, and 326 all ON, the node 321 and thus the RF signal is pulled down to the voltage Voff, which can be, for example, 0.5 volts. The predetermined period that the RMSXDP signal remains high after the RMSMWP signal is set at a low state can correspond to the time period between t1 and t2. In some embodiments, when no row hammer stress mitigation is desired, the RMSXDP signal can be set to a low state at the same time the RMSMWP signal is set at a low state. When the RMSXDP signal is set to a low state, the output of AND gate circuit 314 is set low to isolate the node 321 from the voltage Voff. In addition, the output of NAND gate circuit 316 is set high to turn ON NMOS transistor 332 to pull down the node 321 to the voltage Vnwl (or e.g., Vss or some other low voltage source). As discussed above, the RFF and RF signals generated by the RF driver 310 in coordination with the ARMW and ARMWF signals can be used by MWD 300 to set the global word line voltage.