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Main word line driver circuit

專利號
US10867661B2
公開日期
2020-12-15
申請人
Micron Technology, Inc.(US ID Boise)
發(fā)明人
Tae H. Kim; Christopher J. Kawamura
IPC分類
G11C7/22; G11C11/408; G11C11/4076
技術(shù)領(lǐng)域
word,transistor,gr0,swd,voltage,swds,volts,vnwl,nmos,vccp
地域: ID ID Boise

摘要

A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.

說明書

As discussed above, each of the global word lines (e.g., GR0 to GR3) connects to SWDs in order to quickly drive the signal levels on the respective word lines. FIG. 4B illustrates exemplary embodiment of a SWD array arrangement corresponding to global word lines GR0 and GR1. For clarity, only two sets of SWDs are shown for each global word line GR. For example, SWDs 450 and 460 are connected to global word line GR0, and SWDs 470 and 480 are connected to global word line GR1. However, more than two SWDs can be connected to each global word line GR such as, for example eight SWDs, sixteen SWDs or more. Each of the SWDs 450, 460, 470, and 480 output a local word line WR0, WR1, WR2, and WR3, respectively. As seen in FIG. 4B, the configuration of each of the SWDs 450, 460, 470, and 480 can be the same. Accordingly, for brevity, only the configuration and operation of SWD 450 will be discussed.

權(quán)利要求

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