Operation of the SWD 510 is provided with reference to FIGS. 5A and 5B. At time T0, the processor 116 (and/or another processor) can control the input signals to a FX phase driver (e.g., FXD 600 discussed below) to set the PH0 phase signal to a high state (e.g., Vccp2) and the PHF0 to a low state (e.g., Vnwl). As seen in FIG. 5B, the setting of the PH0 signal to the high state occurs when the global word line is at the pre-charge state such that Vds/Vsd at the time PH0 is at a minimum magnitude, which improves the reliability of SWD 510. After transistor 512 is ON due to PH0 going to the high state, at time T1, the processor 116 (and/or another processor) can control the input signals to MWD (e.g., MWD 300, 410-440, discussed above) to set the value of the global word line GR0 to the active or high state. In some embodiments, the value of the global word line GR is Vccp, which can be, for example, 3.2 volts. With the PHF0 phase signal at the low state, the NMOS transistor 514 is OFF and the local word line WL0 is isolated from the voltage source Vnwl (or, e.g., Vss or another low voltage source). With the PH0 phase signal at the high state, the NMOS transistor 512 pulls up the local word line WL0 to the value Vccp (or another appropriate high state value) of the global word line GR0. In some embodiments, the high state value of the PH0 phase signal is higher than the active state value of the global word line GR0 by at least the threshold voltage of the NMOS transistor 512. For example, if the value of global word line GR0 is 3.2 volts and the threshold value of transistor 512 is 0.6 volts, the PH0 phase signal can be set at a value that 3.8 volts or greater. For example, the PH0 phase signal can be set at a value of Vccp2, which can be in a range of 3.8 volts to 4.7 volts. In some embodiments, the value of Vccp2 can be in a range of 4.2 volts to 4.5 volts, such as, for example, 4.2 volts or 4.5 volts. By setting the value of the PH0 phase signal at or higher than the value of the global word line GR0 plus the threshold voltage of transistor 512 (e.g., Vccp+Vt), the value of the local word line WL0 can be pulled up to the full voltage of the GR0 signal. In some embodiments, the PH0 voltage value is higher than the value of the global word line GR0 plus the threshold voltage of transistor 512 (e.g., greater than Vccp+Vt). That is, the voltage of PH0 is set higher than that the minimum needed for ensuring that the local word line WL0 is at the full voltage of the global word line GR0. However, a higher than minimum required voltage (e.g., greater than Vccp+Vt) can mean that the pull-up transistor in the NMOS-only SWD is less reliable.