Main word line driver circuit
摘要
說明書
After the global word line GR0 has reached the pre-charge state, at time T4, the processor 116 (and/or another processor) can control the input signals to a FX phase driver (e.g., FXD 600 discussed below) to set the PH0 phase signal to a low state having a value Vnwl (or e.g., Vss or some other low voltage value). At this time, the processor 116 (and/or another processor) can control the input signals to a FX phase driver (e.g., FXD 600 discussed below) to set the PHF0 phase signal to a high state having a value Vcc (e.g., 2.5 volts) or Vccp (e.g., 3.2 volts). In some embodiments, the setting of the PHF0 phase signal to the high state can be delayed such that both the PH0 and PHF0 phase signals are at a low value, which means that NMOS transistors 512 and 514 are both off and the local word line WL0 is isolated from both the high and low voltage sources. However, any delay in setting the PHF0 to the high state after the PH0 is set to the low state should be limited since the local word line WL0 will be at a float value. With the PHF0 phase signal at the high state, the transistor 514 is turned on and the value of the local word line WL0 is pulled down to the value of the low voltage source Vnwl (or, e.g., Vss or some other low voltage source). The exemplary timing diagram as shown in
