As discussed above, in some sub-word line drivers (e.g., see FIG. 4B), a PMOS transistor is included in each of the SWDs. The PMOS transistor allows for the word line WL to reach the full high voltage of the global word line GR. For example, if a global word line (e.g., GR0, GR1, GR2, or GR3) is at 3.2 volts, the corresponding local word line (e.g., WL0, WL1, WL2, or WL3) can be pulled up the full 3.2 volts by a PMOS transistor. However, PMOS transistors can require an n-well in a p-well from which the memory cell arrays are formed, thereby causing the layout area for the SWD to be larger. Due the large number of global word lines in a typical memory device, an NMOS-only SWD such as that shown in FIG. 5A reduces the amount of space needed for the SWDs by avoiding the need for an n-well for each of the SWDs, which reduces the area needed by the SWDs on a semiconductor substrate. However, by going to a NMOS-only SWD, full voltage at the local word line (e.g., WL0, WL1, WL2, WL3) may not be achieved unless the gate voltage necessary to couple the voltage from the global word line (e.g., GR0, GR1, GR2, GR3) to the respective local word line (e.g., WL0, WL1, WL2, WL3) is increased by at least the threshold voltage of the NMOS transistors. For example, the embodiment in FIG. 5A, as discussed above, a gate voltage of Vccp2 (e.g., 4.2 volts, 4.5 volts) is applied by the PH0 phase signal instead of a gate voltage of Vccp (e.g., 3.2 volts) used in conventional circuits. Thus, the voltage of the PHn phase signals applied to the gates of the pull-up NMOS transistors in NMOS-only SWDs can be at a higher voltage (e.g., Vccp2) than that (e.g., Vcc, Vccp, etc.) used for the pull-up PMOS transistors in conventional SWDs. In some embodiments, Vccp2 can be in a range of 3.8 volts to 4.7 volts. In some embodiments, the value of Vccp2 can be in a range of 4.2 volts to 4.5 volts, such as, for example, 4.2 volts or 4.5 volts. Conventional FX phase drivers are not able to provide such high PH phase signal voltages without experiencing stability and reliability issues.
