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Main word line driver circuit

專利號
US10867661B2
公開日期
2020-12-15
申請人
Micron Technology, Inc.(US ID Boise)
發(fā)明人
Tae H. Kim; Christopher J. Kawamura
IPC分類
G11C7/22; G11C11/408; G11C11/4076
技術(shù)領(lǐng)域
word,transistor,gr0,voltage,swd,swds,volts,vnwl,nmos,vccp
地域: ID ID Boise

摘要

A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.

說明書

In exemplary embodiments of the present disclosure, FX phase drivers that provide the PHn and PHFn phase signals are configured to reliably provide signal voltages that range from Vnwl to Vccp2 (e.g., ?0.2 volts to 4.7 volts). As seen in FIG. 6, FX driver 600 receives decoded row address signal RF0 and timing control signals R1AC and R2ACF. The processor 116 (and/or another processor) can control the decoded row address signal RF0 and/or the timing control signals R1AC and R2ACF to operate the FX phase driver 600. The circuits (not shown) to generate the timing control signals and the decoded row address signals for FX drivers are known in the art and thus, for brevity, will not be discussed further. As seen in FIG. 6, the FXD 600 includes a phase circuit 610 for generating a PHF phase signal and a phase circuit 620 for generating a PH phase signal that is generally the complement of the PHF phase signal. The phase circuit 610 includes a pull-up circuit 611 and a pull-down circuit 613. In some embodiments, the pull-up circuit 611 can include a transistor 612 and a transistor 618 that are connected in parallel. In some embodiments, the pull-down circuit 613 can include a transistor 614 and a transistor 616 that are connected in series. The transistor 612, which can be, for example, a PMOS transistor, can have a drain coupled to the drain of a transistor 614, which can be, for example, a NMOS transistor. The source of transistor 612 is coupled to a voltage source, such as, for example, Vccp (or, e.g., Vcc or another high voltage source), and the source of transistor 614 is connected to the drain of transistor 616, which can be a NMOS transistor. The source of transistor 616 is coupled to a voltage source, such as, for example, Vnwl (or, e.g., Vss or another low voltage source). As seen in FIG. 6, the interconnected drains of transistors 612 and 614 are coupled to a PHF signal line. In addition, transistor 618, which can be, for example, a PMOS transistor, is connected in parallel with transistor 612. Thus, the source of transistor 618 can be connected to the same voltage source as that of transistor 612, such as, for example, Vccp (or, e.g., Vcc or another high voltage source), and the drain of transistor 618 can be connected to the PHF signal line.

權(quán)利要求

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