Capacitor and method of manufacturing the same
地域：
Suwon-Si
摘要
A capacitor includes a structure including a plurality of openings penetrating from a first surface of the structure to a second surface opposing the first surface; a capacitor layer disposed on the second surface of the structure and in the plurality of the openings and including a dielectric layer, and a first electrode and a second electrode, the dielectric layer interposed between the first electrode and the second electrode; a first connection layer disposed on the first surface of the structure and connected to the first electrode; a second connection layer disposed on the capacitor layer on the second surface and connected to the second electrode of the structure; and first and second terminals disposed on opposite side surfaces of the structure and connected to the first connection layer and the second connection layer, respectively.
說明書
This application claims benefit of priority to Korean Patent Application Nos. 10-2017-0126108 filed on Sep. 28, 2017 and 10-2017-0139478 filed on Oct. 25, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to a capacitor and a method of manufacturing the same.
As electronic devices such as smartphones, wearable devices, and the like are miniaturized, new technologies capable of significantly increasing capacitance of a capacitor, while retaining the same volume, have been developed.
Theoretically, in order to increase capacitance, there are generally three methods. The three methods include a method of using a material having high dielectric permittivity (high-k) as a dielectric, a method of increasing an area in which electrodes face each other, and a method of reducing a thickness of a dielectric layer between the electrodes. Existing representative microcapacitor products each have strategies to achieve high capacitance through a combination of the three methods described above.
In the case of a multilayer ceramic capacitor (MLCC), capacitance thereof may be increased by using a material having high dielectric permittivity of a perovskite structure as a dielectric, connecting a plurality of dielectric layers, repeatedly deposited in parallel to each other, disposing a distance between the electrodes to be close, and reducing a thickness of the dielectric layer.
權(quán)利要求
What is claimed is:1. A capacitor comprising:a structure including a plurality of openings penetrating from a first surface of the structure to a second surface opposing the first surface; a capacitor layer disposed on the second surface of the structure and in the plurality of openings and including a dielectric layer, and a first electrode and a second electrode, the dielectric layer interposed between the first electrode and the second electrode; a filling part comprising a conductor and disposed in a remaining space of the plurality of openings; a first connection layer disposed on the first surface of the structure and connected to the first electrode; a second connection layer disposed on the capacitor layer and connected to the second electrode on the second surface of the structure; first and second terminals disposed on opposite side surfaces of the structure and connected to the first connection layer and the second connection layer, respectively; and a metal layer disposed between the first connection layer and the first electrode, and disposed in each of the plurality of openings. 2. The capacitor of claim 1 , wherein the structure is an anodic aluminum oxide (AAO) structure having the plurality of openings. 3. The capacitor of claim 1 , wherein the dielectric layer includes any one or combination of Al2O3, ZrO2, and HfO2, ora ZrO2— Al2O3— ZrO2 composite layer (ZAZ). 4. The capacitor of claim 1 , wherein the first connection layer is disposed on the first surface of the structure other than a partial region in contact with a second side surface on which the second terminal is disposed, andthe second connection layer is disposed on the second surface of the structure other than a partial region in contact with a first side surface on which the first terminal is disposed. 5. The capacitor of claim 1 , further comprising an insulating layer disposed on a partial region of the second surface of the structure in contact with one of the side surfaces on which the second terminal is disposed to insulate between the second connection layer and the capacitor layer. 6. The capacitor of claim 1 , wherein the filling part is one of tungsten (W) or polycrystalline silicon. 7. The capacitor of claim 1 , further comprising a plurality of bodies stacked on each other,wherein each of the plurality of the bodies includes the structure, the capacitor layer, and the first and second connection layers. 8. The capacitor of claim 1 , wherein the first electrode and the second electrode each include TiN. 9. The capacitor of claim 1 , wherein a distribution of the plurality of openings is in a range of 8.2×108 to 1.6×109 per 1 cm2. 10. The capacitor of claim 1 , wherein each of the plurality of openings has a size of 10 nm to 400 nm. 11. The capacitor of claim 1 , wherein the filling part includes one of tungsten (W) or polycrystalline silicon. 12. The capacitor of claim 1 , wherein the filling part is tungsten (W). 13. A method of manufacturing a capacitor, the method comprising:preparing a structure including a plurality of openings penetrating from a first surface of the structure to a second surface of the structure opposing the first surface of the structure; forming a first connection layer on the first surface of the structure; after the forming of the first connection layer, forming a metal layer by an electroplating process using the first connection layer as a seed layer; forming a capacitor layer disposed on the second surface of the structure and in the plurality of openings and including a dielectric layer, and a first electrode and a second electrode, the dielectric layer interposed between the first electrode and the second electrode; forming a filling part comprising a conductor in a remaining space of the plurality of openings; forming a second connection layer connected to the second electrode on the second surface of the structure; and forming first and second terminals connected to the first connection layer and the second connection layer, respectively, on side surfaces of the structure, wherein the metal layer is disposed between the first connection layer and the first electrode, and is disposed in each of the plurality of openings. 14. The method of claim 13 , further comprising performing anodic oxidation to form the plurality of openings in the structure which is an anodic aluminum oxide (AAO) structure. 15. The method of claim 13 , wherein the first electrode, the dielectric layer, and the second electrode are deposited in order through an atomic layer deposition (ALD) or atomic vapor deposition (AVD) process. 16. The method of claim 13 , wherein the first connection layer is formed on the first surface of the structure so as not to be in contact with a second side surface of the structure on which the second terminal is disposed, andthe second connection layer is formed on the second surface of the structure so as not to be in contact with a first side surface of the structure on which the first terminal is disposed. 17. The method of claim 13 , further comprising forming an insulating layer on a partial region of the second surface of the structure in contact with one of the side surfaces on which the second terminal is disposed. 18. The method of claim 13 , further comprising, stacking a plurality of bodies before the forming of the first and second terminals, each of the plurality of the bodies including the structure, the capacitor layer, and the first and second connection layers.
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