In the capacitor according to an exemplary embodiment in the present disclosure, the porous structure which may be formed by anodic aluminum oxide (AAO) is used, the capacitor layer of the MIM structure is deposited, and the electrodes of the capacitor layer are then connected to the terminals on the opposite side surface of the porous structure. Since the capacitor layer is formed in the plurality of openings, an area of the MIM structure may be increased. As a result, capacitance of the capacitor may be improved. In addition, since the terminals are disposed in directions of the side surfaces of the capacitor, the capacitor may be implemented to have low equivalent series inductance (ESL).

In addition, since the capacitor according to an exemplary embodiment in the present disclosure may be formed in a structure having a thickness of 100 μm or less, the capacitor may be thinned. In addition, assuming that a diameter of the opening is 200 nm, there are openings of 8.2×10⁸ to 1.6×10⁹ per 1 cm², and since the openings may be connected in parallel to each other, the capacitor may be implemented to have the low ESR.

As described above, since the capacitor according to an exemplary embodiment in the present disclosure has a high capacitance single layer structure, the capacitor may be used as a land-side capacitor (LSC) in a chip package requiring a thin thickness.

FIG. 5 is a cross-sectional view illustrating a capacitor including a body stacked according to another exemplary embodiment in the present disclosure.

Bodies including structures, first connection layers, and second connection layers are stacked to form one capacitor.