Selective removal of an etching stop layer for improving overlay shift tolerance
地域：
Hsin-Chu
摘要
An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
說明書
This application claims priority to U.S. Provisional Patent Application Ser. No. 62/692,095 filed Jun. 29, 2018, and entitled “Selective Removal of an Etching Stop Layer for Improving Overlay Shift Tolerance,” the entire disclosure of which is hereby incorporated herein by reference.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
The decreasing geometry sizes lead to challenges in semiconductor fabrication. For example, as pitches between metal components decrease, overlay control becomes more difficult because the same amount of overlay shift now has a more significant impact on device performance (e.g., a misaligned via may cause current leakage between the via and a neighboring metal component). An overlay shift may degrade device performance and/or cause reliability issues. Therefore, while existing semiconductor devices and the fabrication thereof have been generally adequate for their intended purposes, they have not been satisfactory in every aspect.
權(quán)利要求
What is claimed is:1. A method for semiconductor device fabrication, the method comprising:providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component; forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide, wherein the ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD; baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide; and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL, wherein a portion of the conductive component is exposed after the selectively etching of the ESL; and forming a second ESL directly on the exposed portion of the conductive component such that the second ESL physically contacts the conductive component. 2. The method of claim 1 , wherein baking the ESL does not transform the metal oxide located in the first portion of the ESL into metal silicon oxide, and wherein the metal silicon oxide in the second portion of the ESL is formed during the baking by a chemical reaction between the silicon in the ILD and the metal oxide in the second portion of the ESL, and wherein the ESL is baked in an ambient gas comprising nitrogen and hydrogen. 3. The method of claim 2 , wherein the ESL is baked at a temperature between 100 to 400 degree Celsius. 4. The method of claim 1 , wherein the ESL is formed to have a thickness between 10 and 60 Angstroms (A). 5. The method of claim 1 , wherein the metal silicon oxide in the second portion of the ESL is selected from the group consisting of: aluminum silicon oxide (AlSiOx), hafnium silicon oxide (HfSiOx), titanium silicon oxide (TiSiOx), manganese silicon oxide (MnSiOx), and vanadium silicon oxide (VSiOx). 6. The method of claim 1 , wherein the selective etching of the ESL is performed using an etch solution, and wherein the etch solution includes ammonia hydroxide, or hydroxylamine, or both. 7. The method of claim 6 , wherein the etch solution further includes water, a chelator, a metal corrosion inhibitor, as well as a solvent that is selected from the group consisting of diethylene glycol monomethyl ether, ethylene glycol, butyl diethylene glycol, and dimethyl sulfoxide. 8. The method of claim 1 , wherein the selective etching of the ESL is configured such that an etch rate of the first portion of the ESL is substantially greater than an etching rate of the second portion of the ESL. 9. The method of claim 1 , wherein the ILD is a first ILD and the ESL is a first ESL, wherein the forming of the second ESL directly on the exposed portion of the conductive component includes forming the second ESL over the second portion of the first ESL, the method further comprising:forming a second ILD over the second ESL; etching an opening in the second ILD and in the second ESL, wherein the opening is at least partially aligned with the conductive component, wherein the second portion of the first ESL protects a portion of the first ILD located therebelow from being etched; and filling the opening with a conductive material to form a conductive via that contacts the conductive component. 10. The method of claim 9 , further comprising, after forming the second ILD and before etching the opening in the second ILD:forming a capping layer over the second ILD; and forming a hard mask layer over the capping layer, wherein the opening penetrates, from top to bottom, at least the hard mask layer, the capping layer, the second ILD, and the second ESL. 11. A method, comprising:forming a first etch stop layer (ESL) including a first portion in contact with a conductive component and including a second portion in contact with a first interlayer dielectric (ILD) which surrounds the conductive component, wherein the first portion of the first ESL includes metal oxide, and the second portion of the first ESL includes metal silicon oxide; etching the first ESL to remove the first portion of the first ESL but not to remove the second portion of the first ESL; forming a second ESL over the second portion of the first ESL and over the conductive component; forming a second ILD over the second ESL; etching an opening that vertically penetrates through the second ILD and the second ESL to expose an upper surface of the conductive component; and filling the opening with a conductive material to form a conductive via in the opening, wherein the conductive via is in contact with the upper surface of the conductive component but is separated from the first ILD by the second portion of the first ESL. 12. The method of claim 11 , wherein forming the first ESL comprises:depositing the first ESL including metal oxide in the first and second portions but not including any metal silicon oxide in the first and second portions; and baking the first ESL at a temperature between 100 to 400 degree Celsius such that the metal silicon oxide in the second portion of the first ESL is formed by a chemical reaction between silicon in the first ILD and the metal oxide in the second portion of the first ESL. 13. The method of claim 11 , wherein the opening is partially aligned with the conductive component, and wherein the second portion of the first ESL protects the first ILD located therebelow from being etched during etching of the opening. 14. The method of claim 11 , wherein etching the first ESL comprises using a wet etch solution that includes alkali amine, and wherein etching the opening comprises using a dry etch process. 15. A method for making a semiconductor device, comprising:forming first and second conductive components on a substrate; forming an interlayer dielectric (ILD) on the substrate and between the first and second conductive components; forming an etch stop layer (ESL), which comprises a silicon oxide, extending over and in contact with the ILD, wherein the ESL does not extend over either the first conductive component or the second conductive component; and converting a portion of the ESL into metal silicon oxide; and forming a conductive via over and in electrical contact with the first conductive component, wherein the conductive via is separated from the second conductive component by at least the ILD and the metal silicon oxide. 16. The method of claim 15 , further comprising:forming a second ESL over the first ESL and adjacent the conductive via; and forming a second ILD over the second ESL and surrounding the conductive via. 17. The method of claim 16 , wherein the conductive via partially covers an upper surface of the first conductive component, and wherein the second ESL also partially covers the upper surface of the first conductive component. 18. The method of claim 15 , wherein the metal silicon oxide in the ESL is selected from the group consisting of: aluminum silicon oxide (AlSiOx), hafnium silicon oxide (HfSiOx), titanium silicon oxide (TiSiOx), manganese silicon oxide (MnSiOx), and vanadium silicon oxide (VSiOx). 19. The method of claim 15 , wherein the ESL previously extends over either the first conductive component and/or the second conductive component, and is then selectively removed therefrom. 20. The method of claim 15 , wherein the ESL has a thickness between 10 and 60 Angstroms (A).
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