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Selective removal of an etching stop layer for improving overlay shift tolerance

專利號(hào)
US10867805B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Chien-Hua Huang; Tzu-Hui Wei; Cherng-Shiaw Tsai
IPC分類
H01L21/311; H01L21/768; H01L23/528; H01L23/522; H01L21/033; H01L21/8234; H01L21/02; H01L23/532; H01L21/321
技術(shù)領(lǐng)域
esl,ild,conductive,silicon,oxide,etching,in,etch,metal,portion
地域: Hsin-Chu

摘要

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

說(shuō)明書(shū)

In some embodiments, the semiconductor device 100 with the ESL 140 is baked at a temperature between 100 and 400 degrees Celsius. Note that the temperature may vary during baking, for example, according to a predefined temperature profile. In some embodiments, baking lasts between 30 seconds and 10 minutes. In some embodiments, baking may be conducted in an ambient gas including nitrogen (N2), a combination of nitrogen and hydrogen (H2), a combination of nitrogen and an inert gas such as argon (Ar), or any other suitable gas composition. The suitable ambient gas (e.g., N2+H2) helps enhance the silicidation process by making it easier for silicon to penetrate into the ESL portions 142.

Referring now to FIG. 1D, a wet etching process is performed to selectively remove portions of the ESL 140 from the upper surfaces of the semiconductor device 100. In an embodiment, an etch solution 150 is configured such that the ESL portions 142 in contact with the ILD 130 would remain but the ESL portions 144 in contact with the conductive components 120 and 122 would be removed. In other words, post etching the ESL 140 remains on the upper surfaces of the ILD 130, but not on the upper surfaces of the conductive components 120 and 122. As shown in FIG. 1D, a step height profile or geometry is created along the upper surface of the conductive components 120 and 122.

權(quán)利要求

1
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