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Selective removal of an etching stop layer for improving overlay shift tolerance

專(zhuān)利號(hào)
US10867805B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Co., Ltd.（TW Hsinchu）
發(fā)明人
Chien-Hua Huang; Tzu-Hui Wei; Cherng-Shiaw Tsai
IPC分類(lèi)
H01L21/311; H01L21/768; H01L23/528; H01L23/522; H01L21/033; H01L21/8234; H01L21/02; H01L23/532; H01L21/321
技術(shù)領(lǐng)域
esl,ild,conductive,silicon,oxide,etching,in,etch,metal,portion
地域： Hsin-Chu

摘要

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

說(shuō)明書(shū)

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are cross-sectional views of a semiconductor device at various stages of fabrication according to embodiments of the present disclosure.

FIG. 2 is a flow chart of a method for fabricating a semiconductor device in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

權(quán)利要求

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