The present disclosure is generally directed to, but not otherwise limited to, reducing or preventing problems associated with overlay control. Overlay may refer to the alignment between various components of different layers in a semiconductor device such as an integrated circuit (IC) chip. For example, an IC chip may include an interconnect structure that is made up of multiple interconnect layers (also called different metallization layers). Each interconnect layer may include one or more conductive components—such as vias, contacts, or metal lines—that are surrounded by an interlayer dielectric (ILD). In some instances, a first conductive component in one interconnect layer (e.g., an upper layer) may need to be electrically connected to a second conductive component in another interconnect layer (e.g., a lower layer). Thus it is desirable for these two conductive components to be aligned vertically. If overlay control is unsatisfactory, there may be a significant amount of misalignment between the two conductive components, which could lead to problems such as over-etching of the ILD next to the second conductive component (a tiger tooth like pattern). The over-etching may shorten a current leakage pathway to neighboring conductive components, which may in turn cause reliability and/or performance problems such as time-dependent dielectric breakdown (TDDB) or other current leakage issues.