The second insulating layer 40 is a separating layer, which can be a silicon nitride layer or a silicon dioxide layer. The second insulating layer 40 is deposited on the polycrystalline silicon layer 30 and the first insulating layer 20 using chemical vapor deposition.

The first gate electrode layer GE1 is made of a transparent conductive metal such as indium tin oxide (ITO).

The third insulating layer 50 is a medium interlayer, which can be a silicon nitride layer or a silicon dioxide layer. The third insulating layer 50 is deposited on the first gate electrode layer GE1 and the second insulating layer 40 using chemical vapor deposition.

The SD metal layer 60 is made of a transparent conductive metal such as indium tin oxide (ITO). The SD metal layer 60 forms a source electrode 61, a drain electrode 62, and a first metal member 63 that are separated from each other. The first metal member 63 faces the first gate electrode layer GE1 to form a first compensating capacitor C1 therebetween.

The fourth insulating layer 70 and the fifth insulating layer 90 can be a silicon nitride layer or a silicon dioxide layer and are formed by deposition using chemical vapor deposition.

The anode metal layer 80 is made of a transparent conductive metal such as indium tin oxide (ITO).