A drain electrode via 54 and a source electrode via 55 are disposed in the second insulating layer and the third insulating layer. The source electrode of the SI) metal layer is electrically connected to the polycrystalline silicon layer through the source electrode via 55. The drain electrode of the SD metal layer is electrically connected to the polycrystalline silicon layer through the drain electrode via 54. An anode via 71 is disposed in the fourth insulating layer. The anode metal layer is electrically connected to the SD metal layer through the anode via 71. The fifth insulating layer is perforated to form a first via. The light emitting layer is electrically connected to the anode metal layer through the first via.

FIG. 2 is a structural diagram showing an OLED display panel according to some embodiments of the present disclosure. The OLED display panel includes a substrate 10, a first insulating layer 20, a polycrystalline silicon layer 30, a second insulating layer 40, a first gate electrode layer GE1, a third insulating layer 50, a SD metal layer 60, a fourth insulating layer 70, an anode metal layer 80, a fifth insulating layer 90, a photoresist spacer (PS) layer 100, a light emitting layer (not shown), and an cathode layer (not shown).