Trench capacitor and method of forming the same
地域：
Hsinchu
摘要
Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.
說(shuō)明書(shū)
Semiconductor devices that utilize on-chip capacitors include dynamic random access memories (DRAMs), voltage controlled oscillators (VCOs), phase-locked loops (PLL), operational amplifiers (OP-AMPS), and switching (or switched) capacitors (SCs). Such on-chip capacitors are also usable to decouple digital and analog integrated circuits (ICs) from electrical noise generated in or transmitted by other components of a semiconductor device.
Capacitor structures for ICs have evolved from the initial parallel plate capacitor structures, having two conductive layers separated by a dielectric, to more complex capacitor designs for meeting specifications for high capacitance in increasingly smaller devices. These more complex designs include, for example, metal-oxide-metal (MOM) capacitor designs and interdigitated finger MOM capacitor structures. Capacitors utilized in DRAM devices, for example, include stacked capacitors above a substrate or trench capacitors where conductive material extends across a surface of the substrate and/or into multiple trenches.
The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions and spatial relationship(s) of the various features may be arbitrarily enlarged or reduced for clarity. Like reference numerals denote like features throughout specification and drawings.
權(quán)利要求
What is claimed is:1. A method of forming a semiconductor device, the method comprising:depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening and a second trench opening in a substrate; depositing a first conductive layer on the first dielectric layer in both the first trench opening and the second trench opening in the substrate; depositing a second dielectric layer on the first conductive layer in the first trench opening; depositing a second conductive layer on the second dielectric layer in the first trench opening; preventing deposition of the second dielectric layer and the second conductive layer in the second trench opening; planarizing the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer to expose a planarized top surface of the substrate, the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer in the first trench opening; depositing a contact etch stop layer (CESL) overthe planarized top surface, the planarized top surface of the first conductive layer, and the planarized top surface of the second conductive layer; depositing an interlayer dielectric (ILD) layer on the CESL; and forming a first electrical contact through the ILD layer and the CESL to electrically connect to the first conductive layer. 2. The method of claim 1 , wherein the depositing of the first conductive layer comprises depositing the first conductive layer having a thickness that is about 6-times to about 8-times greater than a thickness of the first dielectric layer. 3. The method of claim 1 , further comprising forming a second electrical contact through the ILD layer, wherein the second electrical contact is electrically connected to the second conductive layer in the first trench opening. 4. The method of claim 1 , further comprising forming the first trench opening in the substrate, wherein the first trench opening has an aspect ratio of at least 10. 5. The method of claim 1 , wherein the depositing of the first conductive layer comprises depositing the first conductive layer to a thickness ranging from about 200 angstroms (?) to about 600 ?. 6. The method of claim 1 , wherein the depositing of the first dielectric layer comprises depositing the first dielectric layer having a dielectric constant of at least 7. 7. The method of claim 1 , wherein the depositing of the ILD layer comprises depositing the ILD layer over the first dielectric layer and the first conductive layer in both the first trench opening and the second trench opening. 8. The method of claim 1 , wherein depositing the contact etch stop layer (CESL) further comprises growing a layer of silicon dioxide over the planarized top surface and over the planarized top surface of the first conductive layer. 9. The method of claim 1 , further comprisingrepeating depositing the second dielectric layer and depositing the second conductive layer in only the first trench opening a first number of times, and repeating depositing the second dielectric layer and depositing the second conductive layer in the second trench opening a second number of times, wherein the first number and the second number are different numbers. 10. A method of forming a semiconductor device, comprising:etching a substrate to define a first trench opening in the substrate, wherein the first trench has a first depth in the substrate; etching the substrate to define a second trench opening in the substrate, wherein the second trench has a second depth in the substrate; depositing a first dielectric layer over the substrate, wherein the first dielectric layer extends into the first trench opening and the second trench opening; depositing a first conductive layer on the first dielectric layer, wherein the first conductive layer extends into the first trench opening and the second trench opening; depositing a second dielectric layer over the first conductive layer, wherein the second dielectric layer extends into the first trench opening and the second trench opening; depositing a second conductive layer on the second dielectric layer, wherein the second conductive layer extends into the first trench opening and the second trench opening; repeating depositing the second dielectric layer and depositing the second conductive layer in only the first trench a first number of times; and repeating depositing the second dielectric layer and depositing the second conductive layer in the first trench and the second trench a second number of times, wherein the first number is different from the second number; planarizing the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer to expose a top surface of the substrate, wherein the planarizing comprises defining a first capacitor structure in the first trench opening, and a second trench capacitor structure in the second trench opening; depositing a contact etch stop layer (CESL) on the top surface of the substrate, the first capacitor structure and the second capacitor structure; depositing an interlayer dielectric (ILD) on the CESL; forming a first electrical contact through the ILD layer and the CESL to electrically connect to the first conductive layer in the first capacitor structure; and forming a second electrical contact through the ILD layer and the CESL to electrically connect to the first conductive layer in the second capacitor structure. 11. The method of claim 10 , wherein the etching of the substrate to define the second trench opening comprises etching the substrate after etching the substrate to define the first trench opening. 12. The method of claim 10 , wherein the etching of the substrate to define the second trench opening comprises etching the substrate simultaneously with etching the substrate to define the first trench opening. 13. The method of claim 10 , wherein the etching of the substrate to define the second trench opening comprises defining the second trench have the second depth different from the first depth. 14. A semiconductor device, comprising:a substrate having a top surface; a first multilayer capacitor structure in the substrate, wherein a top surface of the first multilayer capacitor structure is substantially planar with the top surface of the substrate, and the first multilayer capacitor structure comprises N dielectric layers alternating with N conductive layers, wherein N is an integer; and a second multilayer capacitor structure in the substrate, wherein a top surface of the second multilayer capacitor structure is substantially planar with the top surface of the substrate, and the second multilayer capacitor structure comprises M dielectric layers alternating with M conductive layers, wherein M is an integer different from N. 15. The semiconductor device of claim 14 , wherein the first multilayer capacitor structure is electrically connected to the second multilayer capacitor structure. 16. The semiconductor device of claim 14 , whereinthe first multilayer capacitor structure has a first depth, a first width, and a first aspect ratio, the first aspect ratio being equal to the first depth divided by the first width; the second multilayer capacitor structure has a second depth, a second width, and a second aspect ratio, the second aspect ratio being equal to the second depth divided by the second width; and the first aspect ratio is substantially equal to the second aspect ratio. 17. The semiconductor device of claim 16 , wherein at least one of the first aspect ratio and the second aspect ratio is about 10. 18. The semiconductor device of claim 16 , wherein at least one of the first aspect ration and the second aspect ratio is greater than 10. 19. The semiconductor device of claim 14 , wherein the first multilayer capacitor structure and the second multilayer capacitor structure comprise a conductive layer having a thickness not less than 200 ? (?ngstroms) and not greater than 600 ? (?ngstroms). 20. The semiconductor device of claim 19 , wherein the conductive layer has a thickness of about 400 ? (?ngstrom).
意見(jiàn)反饋
使用該功能遇到問(wèn)題
該功能需要專業(yè)版企業(yè)版VIP權(quán)限，您可以：
您也可以聯(lián)系官方QQ: 2157717237 電話: 13264338900