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Trench capacitor and method of forming the same

專利號
US10868107B2
公開日期
2020-12-15
申請人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.(TW Hsinchu)
發(fā)明人
Tao-Cheng Liu; Shih-Chi Kuo; Tsai-Hao Hung; Tsung-Hsien Lee
IPC分類
H01L49/02; H01L21/768; H01L29/94; H01L27/08
技術(shù)領(lǐng)域
trench,layer,dielectric,conductive,capacitor,in,substrate,layers,ild,some
地域: Hsinchu

摘要

Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.

說明書

FIG. 2D is a cross-sectional view of semiconductor device 200 following etching of substrate 102 and removal of trench etch mask 108 in accordance with some embodiments. The portions of substrate 102 exposed by trench etch mask 108 are etched to form one or more trenches 110, 110′. In some embodiments, substrate 102 is etched using plasma etching (PE) or reactive ion etching (RIE). In some embodiments, the trench etch mask 108 remains on substrate 102 (not shown) through additional processing steps until removed during a subsequent CMP process. In some embodiments, one or more cleaning steps follow the formation of trenches 110, 110′ in substrate 102.

Semiconductor device 200 includes two trenches. In some embodiments, the number of trenches is more than two.

權(quán)利要求

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