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Trench capacitor and method of forming the same

專利號(hào)
US10868107B2
公開日期
2020-12-15
申請(qǐng)人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.(TW Hsinchu)
發(fā)明人
Tao-Cheng Liu; Shih-Chi Kuo; Tsai-Hao Hung; Tsung-Hsien Lee
IPC分類
H01L49/02; H01L21/768; H01L29/94; H01L27/08
技術(shù)領(lǐng)域
trench,layer,dielectric,conductive,capacitor,in,substrate,layers,ild,some
地域: Hsinchu

摘要

Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.

說明書

FIG. 2E is a cross-sectional view of semiconductor device 200 following formation of dielectric and conductive layers in accordance with some embodiments. A first dielectric layer 112 is deposited along the exposed surfaces of substrate 102 and the sidewalls and bottom surface of trenches 110 and 110′. In some embodiments where trench mask pattern 108 remains, trench mask pattern 108 is between a top surface of substrate 102 and first dielectric layer 112.

In some embodiments, the first dielectric layer 112 is formed by using chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma CVD, sputtering, atomic layer deposition (ALD), or any other suitable method, or combination of methods, for forming a generally conformal dielectric layer on the exposed surfaces of both the substrate 102 and the trenches 110, 110′. In some embodiments, the first dielectric layer 112 includes a single layer. In some embodiments, the first dielectric layer 112 includes a multilayer structure of one or more suitable dielectric materials. Examples of suitable materials for the first dielectric layer 112 include, but are not limited to, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), SiON, SiC, SiOC, or a combination thereof.

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