FIG. 2F is a cross-sectional view of semiconductor device 200 following filling of trenches 110 and 110′ in accordance with some embodiments. Additional pairs of dielectric layers and conductive layers are sequentially applied to the substrate 102 until a final or top conductive layer 119 is deposited and the trenches 110, 110′ are filled. In some embodiments, each trench 110, 110′ provides the basic structure for a trench capacitor structure containing a predetermined number (N) of dielectric layers and conductive layers. The number of layers, the thickness(es) of the layers, and material(s) comprising the layers selected for filling the trenches 110, 110′, in combination with the dimensions of the trenches, are factors that will determine the level of capacitance provided by the completed trench capacitors. In some embodiments, the predetermined number (N) of dielectric layer and conductive layer pairs utilized to obtain the desired capacitive performance is less than 10. In some embodiments, the predetermined number (N) is between 10 and 20. In some embodiments, the predetermined number (N) is greater than 20.

In some embodiments, a minimum thickness of the conductive layers incorporated into the trench capacitors is selected so as to be within the process control parameters achievable in the subsequent patterning and etching methods. In some embodiments, the thickness of each of the N conductive layers, e.g., 114, 118, 119, is sufficient to allow suitable contact and/or via openings to be patterned and opened to expose contact regions on corresponding N upper surfaces, e.g., 114′, 118′, 119′, of the conductive layers to which electrical contact is established during subsequent processing.