FIG. 2G is a cross-sectional view of semiconductor device 200 following a planarization process in accordance with some embodiments to produce a planarized top surface. The planarization process is used to remove portions of the dielectric layers and conductive layers over substrate 102 and expose a top surface of the substrate. The planarization process defines multilayer trench capacitor structures 120 in trench 110 and multilayer trench capacitor 120′ in the trench 110′. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process to remove portions of each of the previously deposited conductive layers and dielectric layers. The CMP process removes the upper portions of the dielectric layers and conductive layers that extend above and/or over the surface of substrate 102. In some embodiments, a different planarization process, such as etching or grinding, is used to remove the dielectric and conductive layers above substrate 102.

The resulting structure also provides a planarized top surface for subsequent processing and exposes upper surface regions 114′, 118′, 119′ for each of the N conductive layers having a width corresponding to the thickness of each of the deposited conductive layers 114, 118, 119. In some embodiments, the width of the upper surface region 119′ of the final or top conductive layer 119, is larger than the upper surface regions of each of the underlying conductive layers.