FIG. 2H is a cross-sectional view of semiconductor device 200 following deposition of a contact etch stop layer (CESL) 122 in accordance with some embodiments. CESL 122 is formed on the top surface of substrate 102. In some embodiments, CESL 122 is omitted. CESL 122 includes one or more suitable materials including, but not limited to, SiN_x, SiO_x, SiON, SiC, SiCN, BN, SiBN, SiCBN, or combinations thereof. In some embodiments, the CESL 122 is formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, other suitable formation process(es), or combinations thereof.

FIG. 2I is a cross-sectional view of semiconductor device 200 following deposition of an interlayer dielectric (ILD) layer 124. IDL layer 124 is deposited on the CESL 122. In some embodiments where CESL 122 is omitted, the ILD layer 124 is deposited directly on the substrate 102 and upper surface portions 121, 121′ of the trench capacitor structures 120, 120′.

In some embodiments, the ILD layer 124 includes one or more materials including, but not limited to, SiN_x, SiO_x, SiON, SiC, SiCN, BN, SiBN, SiCBN, borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), spin on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced TEOS (PETEOS) or combinations thereof. The ILD layer 124 has a different etch selectivity from CESL 122.