FIG. 5 is a flowchart of a method 500 of making a semiconductor device in accordance with some embodiments. A first mask pattern is formed on a suitable substrate and the exposed regions of the substrate are etched to form a first trench or trench opening, in operation 502. A second mask pattern is formed on the etched substrate and the newly exposed regions of the substrate are etched to form a second trench or trench opening, in operation 504. In some embodiments, the first and second trenches formed in operations 502 and 504 have different depths. In operation 506, a series of alternating dielectric and conductive layers are deposited on the etched substrate to fill the first and second trenches with a predetermined number of pairs of dielectric and conductive layers. In some embodiments, the number of pairs of dielectric and conductive layers used to fill the first trench (N) will be different than the number of pairs of dielectric and conductive layers (M) used to fill the second trench. The resulting structure is planarized, in operation 508, to remove those portions of the alternating dielectric and conductive layers that extend above a plane defined by the substrate surface and form separate first and second multilayer trench capacitor structures in the first and second trenches. In operation 510, a contact etch stop layer (CESL) is deposited on the planarized surface and an interlayer dielectric (ILD) layer is deposited on the CESL. In operation 512, a series of contact openings are then formed through the ILD layer and the CESL to expose surface regions of the conductive layers in both the first and second multilayer trench capacitor structures. A conductive pattern is formed on the ILD layer, in operation 514, in order to establish electrical connections between the first and second multilayer trench capacitor structures and other electrical components.