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Trench capacitor and method of forming the same

專利號(hào)
US10868107B2
公開日期
2020-12-15
申請(qǐng)人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.(TW Hsinchu)
發(fā)明人
Tao-Cheng Liu; Shih-Chi Kuo; Tsai-Hao Hung; Tsung-Hsien Lee
IPC分類
H01L49/02; H01L21/768; H01L29/94; H01L27/08
技術(shù)領(lǐng)域
trench,layer,dielectric,conductive,capacitor,in,substrate,layers,ild,some
地域: Hsinchu

摘要

Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.

說(shuō)明書

In some embodiments, the semiconductor layer(s) incorporated in the substrate 102 are formed using a suitable technique or method including, but not limited to, metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), atomic layer deposition (ALD), and/or combinations thereof.

In some embodiments, the substrate 102 includes both a semiconductor material and an insulating material to form a semiconductor-on-insulator (SOI) substrate. In some embodiments, SOI substrates include one or more semiconductor layers formed on an insulating material such as silicon dioxide or sapphire (silicon-on-sapphire (SOS)). In some embodiments, the substrate 102 includes one or more epitaxial layer (epi-layer) and/or a strained layer resulting from an atomic and/or lattice mismatch.

In some embodiments, one or more dopant(s) are introduced into the substrate during formation of the substrate, in the case of a single-layer substrate, or during formation of one or more layers comprising a multi-layer substrate. In some embodiments, one or more of the semiconductor materials included in a multi-layer substrate are undoped. In some embodiments, one or more of the semiconductor materials are doped with at least one p-type and/or n-type dopant depending on the functional and/or performance target parameters for the semiconductor devices being manufactured on the substrate.

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