In some embodiments, the spacers 150 formed on the sidewalls 130S of the stacked structure 130 in the active region AR and formed on sidewalls of the semiconductor material patterns 135 and 136 in the isolating region IR are formed from the same spacer material layer and through the same etching back process. In some other embodiments, the spacers 150 are formed only on the sidewalls 130S of the stacked structure 130 in the active region AR, while no spacers 150 are formed on sidewalls of the semiconductor material patterns 135 and 136, as the isolating region IR may be masked during the formation of the spacers 150.

In some embodiments, referring to right portion of FIG. 5, source and drain (S/D) regions 160 are formed within the diffusion region 120, in the substrate 100, at both opposite sides of the stacked structure 130 and within the active region AR (e.g. within the transistor region). In certain embodiments, the S/D regions 160 are heavily doped regions with dopants of a conductive type that is the same as that of the LDD region 140 but is different from that of the diffusion region 120. In some embodiments, the diffusion region 120 is an N-well region, and the S/D regions 160 are P-type heavily doped regions. In some embodiments, the diffusion region 120 is a P-well region, and the S/D regions 160 are N-type heavily doped regions. In one embodiment, the S/D regions 160 are heavily doped with dopants as source and drain regions for NMOS and/or PMOS transistors following the CMOS processes. In one embodiment, after the formation of the S/D regions 160, the photoresist pattern PR2 is removed.