Referring to FIG. 6, in some embodiments, silicide top layers 170 are formed on the doped semiconductor material pattern 134, the S/D regions 160 and on the heavily doped portions 135B and 136B by silicidation. In some embodiments, a self-aligned silicide (salicide) process is usually included in a MOS transistor process to reduce the resistance of the S/D regions and silicon gates. In one embodiment, the salicide process includes forming a layer of refractory metal over the substrate 100, thermally reacting the silicon or semiconductor material at the surfaces of S/D regions and of the semiconductor material patterns with the metal to form a metal silicide layer and then removing the unreacted metal. In certain embodiments, the photoresist pattern PR2 is not removed until the self-aligned silicide process is finished. In some embodiments, the regions that are not intended to be formed with silicide are protected by a masking material (not shown), which is later removed. In some embodiments, the material of the silicide top layer 170 is, for example of a non-limiting purpose, a silicide of Ni, Co, Ti, Cu, Mo, Ta, W, Er, Zr, Pt, Yb, Gd, Dy or an alloy of any two thereof. In one embodiment, the material of the silicide top layer 170 is titanium silicide, cobalt silicide, nickel silicide or nickel platinum silicide.