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Semiconductor device having high voltage lateral capacitor and manufacturing method thereof

專利號
US10868108B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Meng-Han Lin; Te-Hsin Chiu; Wei Cheng Wu; Te-An Chen
IPC分類
H01L49/02; H01L27/08; H01L27/06; H01L23/64; H01L21/8234
技術(shù)領(lǐng)域
doped,heavily,in,136a,135b,lightly,capacitor,region,136b,structure
地域: Hsin-Chu

摘要

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having isolation structures therein and a capacitor structure located on a top surface of the isolation structure. The capacitor structure comprises a semiconductor material pattern and an insulator pattern inlaid in the semiconductor material pattern. The semiconductor material pattern and the insulator pattern are located at a same horizontal level on the isolation structure.

說明書

As shown in FIG. 1, in some embodiments, more than one isolation structure 110 is formed in the substrate 100. In certain embodiments, the isolation structures 110 are trench isolation structures. The formation of the trench isolation structures includes partially covering the substrate 100 with a photoresist pattern (not shown), patterning the substrate 100 to form trenches in the substrate 100 and filling the trenches with an insulator material. For example, the photoresist pattern includes a predetermined pattern with openings corresponding to the predetermined locations of the isolation structures. In some embodiments, as shown in FIG. 1, top surfaces 111 of the isolation structures 110 are substantially leveled with the top surface 100S of the substrate 100. In some embodiments, the top surface 100S of the substrate 100 is substantially leveled with the top surface 111 of the isolation structure 110. In one embodiment, after filling the insulator material in the trenches, a planarization process such as a mechanical grinding process or chemical mechanical polishing process is performed to remove extra insulator material. In some embodiments, the insulator material of the isolation structures 110 includes silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. In one embodiment, the insulator material of the isolation structures 110 may be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (SACVD) or by spin-on.

權(quán)利要求

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