High voltage device and manufacturing method thereof
地域：
Zhubei
摘要
A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.
說明書
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The present invention claims priority to TW 107127270 filed on Aug. 6, 2018.
The present invention relates to a high voltage device and a manufacturing method thereof; particularly, it relates to such high voltage device which can avoid turning ON a parasitic transistor therein, and a manufacturing method thereof.
權利要求
What is claimed is:1. A high voltage device comprising:a semiconductor layer, which is formed on a substrate, and has a top surface and a bottom surface opposite to the top surface in a vertical direction; an isolation region, which is formed on and in contact with the top surface, wherein the isolation region is for defining a device region; a deep well which has a first conductivity type and is formed in the semiconductor layer; a buried layer which has a second conductivity type and is formed below the deep well in the semiconductor layer, wherein the buried layer encompasses a lower boundary of the deep well, and is in contact with the deep well; a first high voltage well which has the second conductivity type and is formed on the deep well in the semiconductor layer, wherein the first high voltage well overlays an upper boundary of the deep well and is in contact with the deep well, and the first high voltage well is below and in contact with the top surface in the vertical direction; a first conductivity type well which has the first conductivity type and is formed in the first high voltage well outside the device region, wherein the first conductivity type well is located below and in contact with the top surface in the vertical direction, and wherein the first conductivity type well is in contact with the deep well and is electrically connected to the deep well; a second high voltage well which has the second conductivity type and is formed in the first high voltage well outside the device region, wherein the second high voltage well is located below and in contact with the top surface in the vertical direction, and wherein the second high voltage well is in contact with the buried layer and is electrically connected to the buried layer; a body region which has the first conductivity type and is formed in the first high voltage well within the device region, wherein the body region is located below and in contact with the top surface in the vertical direction; a body contact which has the first conductivity type and is formed in the body region, wherein the body contact is located below and in contact with the top surface in the vertical direction, and wherein the body contact serves as an electrical contact of the body region; a deep well column which has the first conductivity type and is formed in the first high voltage well within the device region, wherein the deep well column is in contact with the deep well and is electrically connected to the deep well, and wherein the deep well column is not in contact with the top surface in the vertical direction; a gate, which is formed on the top surface within the device region, wherein part of the first high voltage well is located below and in contact with the gate in the vertical direction, the gate including:a dielectric layer, which is formed on and in contact with the top surface, and is in contact with the first high voltage well in the vertical direction; a conductive layer, which is formed on and in contact with the dielectric layer, and serves as an electrical contact of the gate; and a spacer layer, which is formed outside of two sidewalls of the conductive layer, and serves as an electrical insulation layer of the gate; and a source and a drain which have the second conductivity type and are formed below and in contact with the top surface in the vertical direction within the device region, wherein the source and the drain are located below and outside two sides of the gate respectively, wherein the side of the gate which is closer to the source is a source side and the side of the gate which is closer to the drain is a drain side, and wherein the source is located in the body region, and the drain is located in the first high voltage well outside the drain side; wherein an inversion region is formed in the body region between the source and the first high voltage well in a channel direction to serve as an inversion current channel in an ON operation of the high voltage device; wherein a drift region is formed in the first high voltage well between the drain and the body region in the channel direction to serve as a drift current channel in the ON operation of the high voltage device; wherein the deep well column is located between the drain and a boundary of the conductive layer near the source side in the channel direction. 2. The high voltage device of claim 1 , further comprising a drift oxide region, which is formed on and in contact with the top surface, and is on and in contact with the drift region within the device region, wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (CVD) structure. 3. The high voltage device of claim 1 , wherein an upper boundary of the deep well column is deeper than a lower boundary of the body region in the vertical direction. 4. The high voltage device of claim 1 , wherein the source, the body region, and the first high voltage well form a parasitic transistor, and the deep well column serves as a minority carriers absorption channel, to avoid turning ON the parasitic transistor. 5. The high voltage device of claim 1 , further comprising:a first conductivity type contact which has the first conductivity type and is formed in the first conductivity type well, wherein the first conductivity type contact is located below and in contact with the top surface in the vertical direction, to serve as an electrical contact of the first conductivity type well; and a second conductivity type contact which has the second conductivity type and is formed in the second conductivity type well, wherein the second conductivity type contact is located below and in contact with the top surface in the vertical direction, to serve as an electrical contact of the second conductivity type well. 6. A manufacturing method of a high voltage device, comprising:forming a semiconductor layer on a substrate, wherein the semiconductor layer has a top surface and a bottom surface opposite to the top surface in a vertical direction; forming an isolation region on the top surface for defining a device region, wherein the isolation region is in contact with the top surface; forming a deep well having a first conductivity type in the semiconductor layer; forming a buried layer having a second conductivity type below the deep well in the semiconductor layer, wherein the buried layer encompasses a lower boundary of the deep well, and is in contact with the deep well; forming a first high voltage well having the second conductivity type on the deep well in the semiconductor layer, wherein the first high voltage well overlays an upper boundary of the deep well and is in contact with the deep well, and wherein the first high voltage well is below and in contact with the top surface in the vertical direction; forming a first conductivity type well having the first conductivity type in the first high voltage well outside the device region, wherein the first conductivity type well is located below and in contact with the top surface in the vertical direction, and wherein the first conductivity type well is in contact with the deep well and is electrically connected to the deep well; forming a second high voltage well having the second conductivity type in the first high voltage well outside the device region, wherein the second high voltage well is located below and in contact with the top surface in the vertical direction, and wherein the second high voltage well is in contact with the buried layer and is electrically connected to the buried layer; forming a body region having the first conductivity type in the first high voltage well within the device region, wherein the body region is located below and in contact with the top surface in the vertical direction; forming a body contact having the first conductivity type in the body region, wherein the body contact is located below and in contact with the top surface in the vertical direction, and wherein the body contact serves as an electrical contact of the body region; forming a deep well column having the first conductivity type in the first high voltage well within the device region, wherein the deep well column is in contact with the deep well and is electrically connected to the deep well, and wherein the deep well column is not in contact with the top surface in the vertical direction; forming a gate on the top surface within the device region, wherein part of the first high voltage well is located below and in contact with the gate in the vertical direction, the gate including:a dielectric layer, which is formed on and in contact with the top surface, and is in contact with the first high voltage well in the vertical direction; a conductive layer, which is formed on and in contact with the dielectric layer, and serves as an electrical contact of the gate; and a spacer layer, which is formed outside of two sidewalls of the conductive layer, and serves as an electrical insulation layer of the gate; and forming a source and a drain having the second conductivity type below and in contact with the top surface in the vertical direction within the device region, wherein the source and the drain are located below and outside two sides of the gate respectively, wherein the side of the gate which is closer to the source is a source side and the side of the gate which is closer to the drain is a drain side, and wherein the source is located in the body region, and the drain is located in the first high voltage well outside the drain side; wherein an inversion region is formed in the body region between the source and the first high voltage well in a channel direction to serve as an inversion current channel in an ON operation of the high voltage device; wherein a drift region is formed in the first high voltage well between the drain and the body region in the channel direction to serve as a drift current channel in the ON operation of the high voltage device; wherein the deep well column is located between the drain and a boundary of the conductive layer near the source side in the channel direction. 7. The manufacturing method of the high voltage device of claim 6 , further comprising: forming a drift oxide region on the top surface, wherein the drift oxide region is in contact with the top surface, and is on and in contact with the drift region within the device region, wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (CVD) structure. 8. The manufacturing method of the high voltage device of claim 6 , wherein an upper boundary of the deep well column is deeper than a lower boundary of the body region in the vertical direction. 9. The manufacturing method of the high voltage device of claim 6 , wherein the source, the body region, and the first high voltage well form a parasitic transistor, and the deep well column serves as a minority carriers absorption channel, to avoid turning ON the parasitic transistor. 10. The manufacturing method of the high voltage device of claim 6 , further comprising:forming a first conductivity type contact which has the first conductivity type in the first conductivity type well, wherein the first conductivity type contact is located below and in contact with the top surface in the vertical direction, to serve as an electrical contact of the first conductivity type well; and forming a second conductivity type contact which has the second conductivity type in the second conductivity type well, wherein the second conductivity type contact is located below and in contact with the top surface in the vertical direction, to serve as an electrical contact of the second conductivity type well.
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