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High voltage device and manufacturing method thereof

專利號
US10868115B2
公開日期
2020-12-15
申請人
RICHTEK TECHNOLOGY CORPORATION(TW Zhubei)
發(fā)明人
Tsung-Yi Huang; Chu-Feng Chen
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L21/762
技術(shù)領(lǐng)域
in,voltage,layer,contact,region,deep,well,type,top,drift
地域: Zhubei

摘要

A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

說明書

Note that, in a preferable embodiment, an upper boundary 25a of the deep well column 25 is deeper than a lower boundary 26b of the body region 26 in the vertical direction. That is, all the deep well column 25 is locate below all the body region 26, and the deep well column 25 is not higher than any part of the body region 26.

Note that the term “inversion current channel” means thus. Taking this embodiment as an example, when the high voltage device 200 operates in ON operation due to the voltage applied to the gate 27, an inversion layer is formed beneath the gate 27, between the source 28 and the drift current channel, so that a conduction current flows through the region of the inversion layer, which is the inverse current channel known to a person having ordinary skill in the art.

Note that the term “drift current channel” means thus. Taking this embodiment as an example, the drift current channel refers to a region where the conduction current passes through in a drifting manner when the high-voltage device 200 operates in ON operation, which is known to a person having ordinary skill in the art.

Note that the top surface 21a as referred to does not mean a completely flat plane but refers to the surface of the semiconductor layer 21′. In the present embodiment, for example, a part of the top surface 21a where the drift oxide region 24 is in contact with has a recessed portion.

權(quán)利要求

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