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High voltage device and manufacturing method thereof

專利號
US10868115B2
公開日期
2020-12-15
申請人
RICHTEK TECHNOLOGY CORPORATION(TW Zhubei)
發(fā)明人
Tsung-Yi Huang; Chu-Feng Chen
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L21/762
技術(shù)領(lǐng)域
in,voltage,layer,contact,region,deep,well,type,top,drift
地域: Zhubei

摘要

A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

說明書

The deep well 411 is formed in the semiconductor layer 41′, and has a first conductivity type. The deep well 411 can be formed by, for example but not limited to, an ion implantation process step which implants first conductivity type impurities into the semiconductor layer 41′ in the form of accelerated ions, to form the deep well 411. The buried layer 412 is formed below the deep well 411 in the semiconductor layer 41′, and has a second conductivity type. The buried layer 412 encompasses the lower boundary of the deep well 411, and is in contact with the deep well 411. The buried layer 412 can be formed by, for example but not limited to, anion implantation process step which implants second conductivity type impurities into the substrate 41 and/or the semiconductor layer 41′ in the form of accelerated ions, to form the buried layer 412. For example, when the semiconductor layer 41′ is an epitaxial layer formed on the substrate 41, the second conductivity type impurities are implanted into the substrate 41 in the form of accelerated ions, and thereafter the epitaxial layer is formed on the substrate 41 by an epitaxial growth process step to form the semiconductor layer 41′, and then the buried layer 412 is formed at or around an interface between the substrate 41 and the semiconductor layer 41′ by a thermal process step, wherein part of the second conductivity type impurities diffuse from the substrate 41 to the semiconductor layer 41′ in the thermal process step to form the buried layer 412.

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