Still referring to FIG. 4, the first high voltage well 42 is formed on the deep well 411 in the semiconductor layer 41′, and has the second conductivity type. The first high voltage well 42 overlays an upper boundary of the deep well 411 and is in contact with the deep well 411, and the first high voltage well 42 is below and in contact with the top surface 41a in the vertical direction. The first conductivity type well 411′ is formed in the first high voltage well 42 outside the device region 43a, and has the first conductivity type. The first conductivity type well 411′ is located below the top surface 41a and in contact with the top surface 41a in the vertical direction. The first conductivity type well 411′ is in contact with the deep well 411 and is electrically connected to the deep well 411. The second high voltage well 412′ is formed in the first high voltage well 42 outside the device region 43a, and has the second conductivity type. The second high voltage well 412′ is located below the top surface 41a and in contact with the top surface 41a in the vertical direction. The second high voltage well 412′ is in contact with the buried layer 412, and is electrically connected to the buried layer 412.