白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

High voltage device and manufacturing method thereof

專利號
US10868115B2
公開日期
2020-12-15
申請人
RICHTEK TECHNOLOGY CORPORATION（TW Zhubei）
發(fā)明人
Tsung-Yi Huang; Chu-Feng Chen
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L21/762
技術(shù)領(lǐng)域
in,voltage,layer,contact,region,deep,well,type,top,drift
地域： Zhubei

摘要

A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

說明書

The gate 47 is formed on the top surface 41a within the device region 43a, wherein part of the first high voltage well 42 is located below and in contact with the gate 47 in the vertical direction. The gate 47 at least includes: a dielectric layer 471, a conductive layer 472, and a spacer layer 473. The dielectric layer 471 is formed on the top surface 41a and in contact with the top surface 41a, and is in contact with the first high voltage well 42 in the vertical direction. The conductive layer 472 is formed on the dielectric layer 471 and in contact with the dielectric layer 471, to serve as an electrical contact of the gate 47. The spacer layer 473 is formed outside of two sidewalls of the conductive layer 472, to serve as an electrical insulation layer of the gate 47.

權(quán)利要求

1
微信群二維碼
意見反饋