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High voltage device and manufacturing method thereof

專利號(hào)
US10868115B2
公開日期
2020-12-15
申請(qǐng)人
RICHTEK TECHNOLOGY CORPORATION(TW Zhubei)
發(fā)明人
Tsung-Yi Huang; Chu-Feng Chen
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L21/762
技術(shù)領(lǐng)域
in,voltage,layer,contact,region,deep,well,type,top,drift
地域: Zhubei

摘要

A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

說明書

This embodiment differs from the first embodiment in that, in the first embodiment, the drift oxide region 24 is a LOCOS structure, while in this embodiment, the high voltage device 500 does not include any drift oxide region on the drift region 52a. The lateral distance (length of the drift region 52a) between the body region 56 and the drain 59 of the high voltage device 500 is determined according to the operation voltage that the device is required to operate with.

Please refer to FIGS. 6A to 6G, which show a fifth embodiment of the present invention. This embodiment shows schematic diagrams of a manufacturing method of the high voltage device 200 according to the present invention. FIG. 6B shows a schematic diagram of a cross-section view according to the cross-section line A-A′ shown in FIG. 6A. As shown in FIGS. 6A and 6B, first, the semiconductor layer 21′ is formed on the substrate 21, wherein the semiconductor layer 21′ has a top surface 21a and a bottom surface 21b that is opposite to the top surface 21a in the vertical direction (as indicated by the direction of the solid arrow in FIG. 6B). The substrate 21 is, for example but not limited to, a P-type or N-type silicon substrate. The semiconductor layer 21′, for example, is formed on the substrate 21 by an epitaxial growth process step, or a part of the substrate 21 is used as the semiconductor layer 21′. The semiconductor layer 41′ can be formed by any method known to a person having ordinary skill in the art, so the details thereof are not redundantly explained here.

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