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High voltage device and manufacturing method thereof

專利號
US10868115B2
公開日期
2020-12-15
申請人
RICHTEK TECHNOLOGY CORPORATION(TW Zhubei)
發(fā)明人
Tsung-Yi Huang; Chu-Feng Chen
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L21/762
技術(shù)領(lǐng)域
in,voltage,layer,contact,region,deep,well,type,top,drift
地域: Zhubei

摘要

A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

說明書

Still referring to FIGS. 6A and 6B, next, the isolation structure 23 and the drift oxide region 24 are formed on the top surface 21a and in contact with the top surface 21a. The isolation structure 23 is for defining the device region 23a (as indicated by a dashed frame shown in FIG. 6A). The isolation structure 23 is not limited to the local oxidation of silicon (LOCOS) structure as shown in the figure; in other embodiments, it may be a shallow trench isolation (STI) structure instead. The drift oxide region 24 is formed on the top surface 21a and in contact with the top surface 21a. The drift oxide region 24 is located on the drift region 22a (as indicated by the dashed frame shown in FIG. 2) within the device region 23a, and is in contact with the drift region 22a.

權(quán)利要求

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