This is a non-provisional application of and claims priority to U.S. Provisional Patent Application Ser. No. 62/593,049, entitled “Circuit Structure and Method for Reducing Noises” and filed Nov. 30, 2017, the entire disclosure of which is hereby incorporated by reference.

An integrated circuit (IC) includes various devices (e.g., transistors, diodes, and resistors) connected together and configured to work as a functional circuit. In existing field effect transistors (FETs), different materials come into contact in a channel, creating various interface areas. For example, a channel has a horizontal interface with an overlaying gate dielectric layer and vertical interfaces with isolation features that extend into the channel from the sides. During field application, charge carriers (electrons or holes) travelling in the channel between a source and a drain are affected by such interfaces as the charge carriers get trapped and detrapped at the interfaces. The fluctuation in carrier mobility tends to generate or increase electronic noises, such as flicker noise and random telegraph signal (RTS) noise. Flicker noise (sometimes called 1/f noise or pink noise) is a low frequency noise that may exhibit an inverse frequency power density curve. RTS noise (sometimes called burst noise, popcorn noise, impulse noise, bi-stable noise) may cause sudden changes in channel current at random and unpredictable times. Although certain measures such as thinning down the gate dielectric thickness may reduce noises, a thinner gate dielectric layer may degrade performance of a transistor, for example, in high-voltage applications. Thus, a new device structure is desired to address the above concerns in high-voltage and other transistor applications.