The gate stack 114 may be formed by various deposition techniques following a proper procedure, such as a gate-last process, wherein a dummy gate is first formed and is then replaced by a metal gate after forming source and drain. Alternatively, the gate stack 114 may be formed by high-k-last process, where both the gate dielectric material layer 116 and the gate electrode 120 are replaced by a high-k dielectric material and metal, respectively, after forming source and drain. The gate stack 114 may further include on its sidewalls a gate spacer 122. In some embodiments, the gate spacer 122 is considered as attached to the gate stack 114 and separating the gate stack 114 from other structures such as the isolation region 104. The spacer 122 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric material, or a combination thereof. The spacer 122 may have a multilayer structure and may be formed by depositing dielectric material and then anisotropic etching, such as plasma etching. One exemplary gate stack 114 and the method of making the same are further described below in accordance with some embodiments.

The semiconductor structure 100 includes a channel region 124 defined on the active region 106 and underlying the gate stack 114. The channel region 124 may be tuned for proper threshold voltage or other parameters by ion implantation. The channel region 124 has a same type of dopant to that of the doped well 110 but at a greater concentration, depending on the application and device specification. In the present example for nFET, the channel region 124 is doped with a p-type dopant.