Although FIGS. 1A-1C illustrate the source 126 and the drain 128 as somewhat symmetrically disposed on both sides of the channel region 124, in some embodiments the source 126 and the drain 128 are configured asymmetrically (e.g., for some high voltage applications). The drain 128, as a high voltage is applied during the field applications, may be spaced further away from the gate stack 114, thus the high voltage is able to be distributed in the region between the gate and the drain 128 to reduce high voltage damages to the device. The source 126 may be configured closer to the gate stack 114, such that an edge of the source 126 is aligned to an edge of the gate stack 114, as illustrated in FIG. 1A. The formation of the source 126 and the drain 128 may include forming a patterned mask to define source and drain regions, and implantation or epitaxial growth to form the source 126 and the drain 128. The source 126 may further include silicide on its top surface to reduce contact resistance. For example, silicide on the source 126 may be formed by a self-aligned silicide procedure that further includes depositing a metal (such as nickel, cobalt, titanium or other suitable metal) on the source; annealing to react the metal with silicon of the source 126 to form metal silicide; and etching to remove unreacted metal.