Although the active region 106 and the gate stack 114 are illustrated herein as having regular shapes with straight edges, other suitable shapes with polygonal or curve lines are contemplated by the present disclosure. For example, the corner portions 114A-114D may have rounded or straight corners. FIG. 1D shows that the corner portions 114A-114D have a normal angle of 90 degrees (denoted as angle “M”), but this angle may have another value. The active region 106 may or may not have a normal angle (denoted as angle “N”) at the juncture between its middle portion 106A and left and right portions 106B or 106C. Depending on the shape of the active region 106 and the gate stack 114, methods of measuring the various dimensions disclosed herein may vary accordingly.

The various FET structures disclosed herein may have any suitable size or dimension. In some embodiments, when used for analog and radio frequency (RF) applications an FET may have relatively large sizes (e.g., at least hundreds of nanometers in width or length). For example, a, b, c1, and c2 shown in FIG. 1D may each be in the range of 0.03 to 0.3 micrometer (um). Depending on the design, each of a, b, c1, and c2 may be the same or may be different from one another. In some embodiments, L2 is 0.3 um or more (e.g., 0.3-1 um).