FIG. 2 is a flowchart of the method 200 for making an IC device having an FET. The method 200 is described in connection with FIGS. 3A-3E, which are the same sectional view as FIG. 1B but represent intermediate stages of the semiconductor structure 100 before leading to the semiconductor structure 100 shown in FIG. 1B. In operation 210, a starting semiconductor structure is provided, which includes the substrate 102, the isolation features 104A and 104B on the substrate 102, and the active region 106, as shown in FIG. 3A. The isolation features 104A and 104B at least partially surround and define the active region 106. The formation of the isolation features 104A and 104B may include forming a patterned mask by lithography; etching the substrate 102 through the openings of the patterned mask to form trenches; filling the trench with one or more dielectric material; and performing a CMP process. In some embodiments, the active region 106 may be three-dimensional, such as fin active regions. In this case, the operation 202 may further includes selective etching to recess the isolation features 104A and 104B or selective epitaxial growth to the active regions with one or more semiconductor material.