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Circuit structure and method for reducing electronic noises

專利號(hào)
US10868116B2
公開日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Ching-Hung Kao; Chi-Feng Huang; Fu-Huan Tsai; Victor Chiang Liang
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L29/10
技術(shù)領(lǐng)域
ldd,gate,stack,region,isolation,drain,doping,in,feature,hdd
地域: Hsinchu

摘要

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

說明書

According to other embodiments, the present disclosure provides a method for semiconductor fabrication comprising providing a semiconductor structure including a substrate, an isolation region on the substrate, and an active region that is at least partially surrounded by the isolation region. The method further comprises forming a gate stack over the active region, the gate stack including a gate dielectric layer and a gate electrode layer disposed above the gate dielectric layer. The method further comprises forming an LDD feature that separates an edge portion of the gate dielectric layer from the isolation region, and forming a spacer on sidewalls of the gate stack directly above the LDD feature. In an embodiment, the edge portion of the gate dielectric layer is between two corner portions of the gate dielectric layer. The LDD feature does not separate the two corner portions of the gate stack from the isolation region. The two corner portions of the gate dielectric layer extend laterally into the isolation region. In an embodiment, the method further comprises forming an HDD feature that separates the LDD feature and the spacer from the isolation region. In an embodiment, the LDD feature and the HDD feature are formed on a first side of the gate stack. The method further comprises forming a second LDD feature but no additional HDD feature on a second side of the gate stack opposite to the first side of the gate stack. In an embodiment, the LDD feature and the HDD feature are formed using separate ion implantation processes. The LDD feature has a doping concentration at least twice as high as that of a channel region underneath the gate stack, and the HDD feature includes a doping concentration that is at least 10 times as high as that of the LDD feature.

權(quán)利要求

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