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Circuit structure and method for reducing electronic noises

專利號
US10868116B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Ching-Hung Kao; Chi-Feng Huang; Fu-Huan Tsai; Victor Chiang Liang
IPC分類
H01L29/06; H01L29/66; H01L29/78; H01L29/10
技術(shù)領域
ldd,gate,stack,region,isolation,drain,doping,in,feature,hdd
地域: Hsinchu

摘要

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

說明書

The foregoing has outlined features of several embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

權(quán)利要求

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