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Method for forming apparatus comprising two dimensional material

專利號
US10868121B2
公開日期
2020-12-15
申請人
Nokia Technologies Oy(FI Espoo)
發(fā)明人
Darryl Cotton; Yinglin Liu; Adam Robinson; Alexander Bessonov; Richard White
IPC分類
H01L29/16; H01L29/66; H01L29/778; H01L31/028; H01L29/12; H01L29/06; H01L29/417; H01L29/423; G01N27/414; H01L31/112
技術領域
mouldable,layer,graphene,material,release,may,polymer,electrodes,two,be
地域: Espoo

摘要

A method and apparatus, the method comprising: forming a layer of two dimensional material (23), in particular graphene, on a first release layer; forming, possibly a (gate) insulating layer (35), and at least two, preferably three, electrodes (25); forming a second release layer overlaying at least a portion of the layer of two dimensional material; providing a mouldable polymer (24, 26, 28) overlaying the at least two electrodes and the second release layer; and removing the first and second release layers to provide a cavity (29) between the mouldable polymer (26) and the layer of two dimensional material (23).

說明書

In the examples of FIGS. 3A to 3I the apparatus 21 comprises a bottom gate FET. It is to be appreciated that the methods could be modified to provide an apparatus 21 comprising a top gate FET. For instance the gate electrode of the top gate FET could be deposited on the surface of the moldable polymer 27 after the first release layer 33 has been removed. Other apparatus 21 could be formed using other similar methods.

FIG. 4 is a plan view of another example apparatus 21. The example apparatus of FIG. 4 may be formed using the methods described above. The apparatus 21 comprises a layer of two dimensional material 23, a plurality of electrodes 25 moldable polymer 27 and a discontinuity 29 which may be as described above. Corresponding reference numerals are used for corresponding features. The plurality of electrodes 25 and the layer of two dimensional material 23 are arranged to form an FET.

權利要求

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