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Silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device

專利號
US10868122B2
公開日期
2020-12-15
申請人
FUJI ELECTRIC CO., LTD.(JP Kawasaki)
發(fā)明人
Takeshi Tawara; Koji Nakayama; Yoshiyuki Yonezawa; Hidekazu Tsuchida; Koichi Murata
IPC分類
H01L29/16; H01L29/868; H01L29/66
技術(shù)領(lǐng)域
layer,type,drift,lifetime,epitaxial,carbide,silicon,vanadium,region,in
地域: Kawasaki

摘要

During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 μm from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.

說明書

Further, in “Low Loss 4H—SiC PiN Diode with Local Low Carrier Lifetime Region” (K Nakayama, et al.), in the n?-type drift layer, provision of a low carrier lifetime layer at a position separated from the pn junction surface between the p-type anode layer and the n?-type drift layer, and use of vanadium as an example of an element doped in the low carrier lifetime layer are described. Nonetheless, in “Low Loss 4H—SiC PiN Diode with Local Low Carrier Lifetime Region” (K Nakayama, et al.), no method of managing whether the carrier lifetime of the low carrier lifetime layer is set within an allowable range of the design value is described.

Embodiments of a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or ? appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or ?. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described.

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