For example, a surface of the second p-type layer 305 may be exposed at the front surface of the semiconductor substrate 320 by a recess 13′ (concave on the p-type starting substrate 301 side) at which an edge termination region 32 side of the active region 31 is lower than a center portion side of the active region 31. The p+-type gate contact region 307 may be selectively provided in a surface layer of the second p-type layer 305, the surface layer having the exposed surface in the active region 31. An n+-type cathode contact region 308 is selectively formed in the second n-type layer 306. The second n-type layer 306 is in contact with a cathode electrode 314 via the n+-type cathode contact region 308 and is at an electric potential K of the cathode electrode 314. The p-type starting substrate 301 is in contact with an anode electrode 315 and is at an electric potential A of the anode electrode 315.