Silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device
摘要
說(shuō)明書
Next, a process that includes a photolithography process and ion implantation as one set is repeatedly performed, whereby the p+-type gate contact region 307 is selectively formed in the second p-type layer 305. The n+-type cathode contact region 308 is selectively formed in the second n-type layer 306. Additionally, plural p-type regions constituting the edge termination structure 309 are selectively formed in the third n?-type layer 312. Then, all the regions that are formed by ion implantation are activated by thermal activation annealing in an argon atmosphere. Thereafter, by a general method, a field oxide film (not depicted), the cathode electrode 314, the anode electrode 315, and the gate electrode 313 are formed, whereby the IGBT depicted in
As described, according to the embodiments above, the n?-type lifetime reduced layer that is doped with vanadium as a carrier lifetime killer is provided in the n?-type drift layer, at a position that is deeper from the pn junction surface between the p-type anode layer and the n?-type drift layer in a direction toward the cathode side than is a predetermined depth. The carrier lifetime of the lifetime reduced layer that is selectively formed in the n?-type drift layer, as described above, is measurable by CV measurement and therefore, quality of the carrier lifetime of the lifetime reduced layer may be evaluated by non-destructive inspection (inspection to evaluate the internal structure of the semiconductor chip without cutting, etc.).
