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Semiconductor devices including field effect transistors and methods of forming the same

專利號
US10868125B2
公開日期
2020-12-15
申請人
Samsung Electronics Co., Ltd.
發(fā)明人
Mirco Cantoro; Zhenhua Wu; Krishna Bhuwalka; Sangsu Kim; Shigenobu Maeda
IPC分類
H01L29/267; H01L27/092; H01L27/088; H01L21/8234; H01L21/8238; H01L29/10; H01L29/16; H01L29/165; H01L21/02; H01L29/06
技術(shù)領(lǐng)域
doped,pattern,layer,graphene,may,buffer,ap2,ap1,patterns,active
地域： Suwon-si

摘要

A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

說明書

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. patent application Ser. No. 15/591,405, filed on May 10, 2017, which is a divisional application of U.S. patent application Ser. No. 14/823,229, filed on Aug. 11, 2015, now U.S. Pat. No. 9,679,975, issued on Jun. 13, 2017, which claims the benefit of Korean patent application number 10-2014-0159871, filed on Nov. 17, 2014, in the Korean Intellectual Property Office, the contents of which applications are incorporated herein in their entirety by reference.

BACKGROUND

The inventive concepts relate to semiconductor devices and methods of forming the same. More particularly, the inventive concepts relate to semiconductor devices including field effect transistors and methods of forming the same.

Semiconductor devices are widely used in the electronic industry because of their small sizes, multi-functional characteristics, and/or low manufacture costs. Semiconductor devices may be categorized as any one of semiconductor memory devices storing data, semiconductor logic devices processing operations of logical data, and hybrid semiconductor device having both the function of the semiconductor memory devices and the function of the semiconductor logic devices. High-reliable, high-speed, and/or multi-functional semiconductor devices have been increasingly demanded. To satisfy these demands, structures of semiconductor devices have been complicated and semiconductor devices have been highly integrated.

SUMMARY

Exemplary embodiments in accordance with principles of inventive concepts may provide semiconductor devices capable of improving operating characteristics and reliability and methods of forming the same.

權(quán)利要求

1
What is claimed is:1. A semiconductor device comprising:an active pattern on a substrate, the active pattern defined by a device isolation layer; anda gate electrode on the active pattern and intersecting the active pattern,wherein the active pattern comprises:a first buffer pattern on the substrate;a channel pattern on the first buffer pattern;a doped pattern between the first buffer pattern and the channel pattern; anda second buffer pattern between the doped pattern and the channel pattern,wherein the doped pattern provides extra carriers to the channel pattern, andwherein a height of a bottom surface of the device isolation layer is lower than a height of a bottom surface of the first buffer pattern, and a height of a top surface of the device isolation layer is lower than a height of a bottom surface of the doped pattern such that an upper portion of the first buffer pattern is exposed by the device isolation layer.2. The semiconductor device of claim 1, wherein the doped pattern has a conductivity type of a P-type or an N-type.3. The semiconductor device of claim 1 wherein the doped pattern includes graphene injected with an impurity.4. The semiconductor device of claim 3, wherein the doped pattern has a crystal structure formed by substituting the impurity for some of carbon atoms of graphene.5. The semiconductor device of claim 3, wherein an impurity concentration of the doped pattern is higher than 1×106/cm and equal to or lower than 1×1012/cm.6. The semiconductor device of claim 1, wherein the first buffer pattern and the second buffer pattern include the same material.7. The semiconductor device of claim 1, wherein the active pattern further comprises: a barrier pattern on the channel pattern,wherein the channel pattern is disposed between the second buffer pattern and the barrier pattern, andwherein the channel pattern includes a material of which an energy band gap is smaller than those of the second buffer pattern and the barrier pattern.8. The semiconductor device of claim 7, wherein the channel pattern includes a III-V group compound.9. The semiconductor device of claim 1, wherein the active pattern includes an upper portion exposed by the device isolation layer, andwherein the doped pattern is in the upper portion of the active pattern.10. A semiconductor device comprising:an active pattern on a substrate;a device isolation layer on the substrate and on a side surface of the active pattern, the active pattern including an active fin exposed by the device isolation layer; anda gate electrode on the active pattern and intersecting the active pattern, the gate electrode covering top and side surfaces of the active fin and extending onto a top surface of the device isolation layer,wherein the active pattern comprises:a first buffer pattern on the substrate;a channel pattern on the first buffer pattern;a doped pattern between the first buffer pattern and the channel pattern; anda second buffer pattern between the doped pattern and the channel pattern,wherein the doped pattern includes graphene layer injected with impurities, and the doped pattern provides extra carriers to the channel pattern,wherein the doped pattern is in direct contact with the first buffer pattern, andwherein a height of the top surface of the device isolation layer is lower than a height of a bottom surface of the doped pattern such that an upper portion of the first buffer pattern is exposed by the device isolation layer, and a lower portion of the first buffer pattern is covered by the device isolation layer.11. The semiconductor device of claim 10, wherein the doped pattern has a crystal structure that some of carbon atoms of the graphene layer is substituted by the impurities.12. The semiconductor device of claim 10, wherein the active fin includes the doped pattern.13. The semiconductor device of claim 10, wherein the first buffer pattern and the second buffer pattern include the same material.14. The semiconductor device of claim 10, wherein a height of a bottom surface of the device isolation layer is lower than a height of a bottom surface of the first buffer pattern.15. The semiconductor device of claim 10, wherein a height of the top surface of the device isolation layer is higher than a top surface of the substrate and the height of the top surface of the device isolation layer is below a top of the first buffer pattern.16. The semiconductor device of claim 1, wherein a height of the top surface of the device isolation layer is higher than a top surface of the substrate and the height of the top surface of the device isolation layer is below a top of the first buffer pattern.
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