白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Semiconductor devices including field effect transistors and methods of forming the same

專利號(hào)
US10868125B2
公開日期
2020-12-15
申請(qǐng)人
Samsung Electronics Co., Ltd.
發(fā)明人
Mirco Cantoro; Zhenhua Wu; Krishna Bhuwalka; Sangsu Kim; Shigenobu Maeda
IPC分類
H01L29/267; H01L27/092; H01L27/088; H01L21/8234; H01L21/8238; H01L29/10; H01L29/16; H01L29/165; H01L21/02; H01L29/06
技術(shù)領(lǐng)域
doped,pattern,layer,graphene,may,buffer,ap2,ap1,patterns,active
地域： Suwon-si

摘要

A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

說明書

In some exemplary embodiments, even though not shown in the drawings, the active pattern AP may be provided in plurality. In such embodiments, one gate electrode GE may intersect the plurality of active patterns AP. Each of the active patterns AP may include the first buffer pattern 102, the doped pattern 104, the second buffer pattern 106, and the channel pattern 108. Each of the active patterns AP may further include the barrier pattern 112. The doped patterns 104 of the plurality of active patterns AP may have the same conductivity type.

A gate insulating pattern GI may be provided between the gate electrode GE and the active pattern AP. The gate insulating pattern GI may extend along a bottom surface of the gate electrode GE in the second direction D2. According to exemplary embodiments, the gate insulating pattern GI may be in contact with the top surface of the active pattern AP and the top surface of the device isolation layer ST, as illustrated in FIG. 1C. Alternatively, the gate insulating pattern GI may be in contact with the top surface and the exposed sidewalls of the active pattern AP and may extend onto the top surface of the device isolation layer ST so as to be in contact with the top surface of the device isolation layer ST, as illustrated in FIG. 1D.

A capping pattern CAP may be provided on a top surface of the gate electrode GE, and gate spacers GS may be provided on both sidewalls of the gate electrode GE.

權(quán)利要求

1
微信群二維碼
意見反饋