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Semiconductor devices including field effect transistors and methods of forming the same

專利號
US10868125B2
公開日期
2020-12-15
申請人
Samsung Electronics Co., Ltd.
發(fā)明人
Mirco Cantoro; Zhenhua Wu; Krishna Bhuwalka; Sangsu Kim; Shigenobu Maeda
IPC分類
H01L29/267; H01L27/092; H01L27/088; H01L21/8234; H01L21/8238; H01L29/10; H01L29/16; H01L29/165; H01L21/02; H01L29/06
技術(shù)領(lǐng)域
doped,pattern,layer,graphene,may,buffer,ap2,ap1,patterns,active
地域： Suwon-si

摘要

A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

說明書

Referring to FIGS. 9A, 9B, 9C, and 9D, a device isolation layer ST defining a plurality of active patterns AP1 and AP2 may be provided on a substrate 100. The active patterns AP1 and AP2 may include a first active pattern AP1 and a second active pattern AP2 that are spaced apart from each other with the device isolation layer ST interposed therebetween. Each of the active patterns AP1 and AP2 may have a bar shape extending in a first direction D1. The active patterns AP1 and AP2 may be spaced apart from each other in a second direction D2 intersecting the first direction D1.

Each of the active patterns AP1 and AP2 may include a first buffer pattern 102 on the substrate 100, a channel pattern 108 on the first buffer pattern 102, and a second buffer pattern 106 between the first buffer pattern 102 and the channel pattern 108. In an exemplary embodiment, each of the active patterns AP1 and AP2 may further include a barrier pattern 112 disposed on the channel pattern 108. In such exemplary embodiments, the channel pattern 108 may be disposed between the barrier pattern 112 and the second buffer pattern 106.

According to the present exemplary embodiment, the first active pattern AP1 may include a first doped pattern 104a disposed between the first and second buffer patterns 102 and 106 of the first active pattern AP1, and the second active pattern AP2 may include a second doped pattern 104b disposed between the first and second buffer patterns 102 and 106 of the second active pattern AP2.

權(quán)利要求

1
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