According to an exemplary embodiment, both sidewalls of each of the active patterns AP1 and AP2 may not be exposed by the device isolation layer ST, as illustrated in FIG. 9D. Alternatively, each of the active patterns AP1 and AP2 may have an upper portion (e.g., an active fin AF) exposed by the device isolation layer ST, as illustrated in
A gate electrode GE may be provided to intersect the active patterns AP1 and AP2. According to an exemplary embodiment, one gate electrode GE may intersect the plurality of active patterns AP1 and AP2, as illustrated in