Referring again to FIGS. 9A, 9B, 9C, and 9D, a gate electrode GE intersecting the active patterns AP1 and AP2 may be formed on the substrate 100. The gate electrode GE may be provided on the active patterns AP1 and AP2 and may extend in the second direction D2. In an exemplary embodiment, the gate electrode GE may cover the top surfaces of the active patterns AP1 and AP2 and the top surface of the device isolation layer ST, as illustrated in FIG. 9D. In another exemplary embodiment, the gate electrode GE may cover the top surfaces and the exposed sidewalls of the active patterns AP1 and AP2 and may extend onto the top surface of the device isolation layer ST, as illustrated in FIG. 9E. A gate insulating pattern GI may be formed between the gate electrode GE and the active patterns AP1 and AP2. A capping pattern CAP may be formed on a top surface of the gate electrode GE, and gate spacers GS may be formed on both sidewalls of the gate electrode GE. In exemplary embodiments in accordance with principles of inventive concepts, the gate insulating pattern GI, the gate electrode GE, the capping pattern CAP, and the gate spacers GS may be formed by the substantially same method as described in the first embodiment with reference to FIGS. 1A to 1C. Thereafter, source/drain regions 110 may be formed in the active patterns AP1 and AP2 at both sides of the gate electrode GE.
